Compiled language (Royal Chia 4 edition) - complete curriculum and review notes

For examination/end-of-cycle review,** chapter structure is fully consistent with Wang Chong Chong ’ s Catalogue of Languages (4th edition)**: chapter 17 + chapter experiment/course design + comprehensive studies + note 1 ~4. The CPU model is 8086 (16 bits, real mode). All code examples and calculations in the text have been tested on a case-by-case basis.

Contents

1. 基础知识
2. 寄存器
3. 寄存器(内存访问)
4. 第一个程序
5. [[BX] and Loop Directives] (#5-bx and Loop Directives)
6. 包含多个段的程序
7. 更灵活的定位内存地址的方法
8. 数据处理的两个基本问题
9. 转移指令的原理
10. CALL和RET指令
11. 标志寄存器
12. 内中断
13. int指令
14. 端口
15. 外中断
16. 直接定址表
17. 使用BIOS进行键盘输入和磁盘读写
18. 综合研究
19. 附注
20. 复习速查（本笔记补充）

1. Basic knowledge

1.1 Machine language

• ** Machine language**: The collection of binary machine commands, CPU can be executed directly, but people can hardly read and write directly.
• The compilation language is based on the machine language and is supported by symbols.

1.2 Generation of compilation languages

• Machine language is hard to remember, difficult to check, so use ** amulet** (e.g. mov、addThis is the motivation for compiling the language.

1.3 Composition of compilation languages

The compilation language consists of three types of instructions:

1. ** Compiled directive**: the machine code identifier, which is the core of the compilation language and has the corresponding machine code;
2. ** Hypocrisy directive**: no corresponding machine code, performed by a compiler segment、end）；
3. ** Other symbol**: if +、-、*、/, identified by compiler, without corresponding machine code.

1.4 Storage

• ** Storer**: Parts of CPU that read/written data when running, consisting of several ** storage units**.
• Role of memory: Storage of ** Directives and data required for CPU implementation**.

1.5 Instructions and data

• ** The instructions and data memory/disk do not differ, and are binary information**; the CPU treats the information at work as a directive and some as data, and the difference is only in ** application**.

1.6 Storage units

• Storage units are divided into several storage units, each numbered from 0 to ** address**.
• 8086 A storage unit = 1 bytes (byte) = 8 bit; 1 word (Word) = 2 bytes.

1.7 CPU for memory reading and writing

To read and write data, CPU must interact 3 types of information with an external chip:

1. ** Address information**: address of the storage unit (through address bus);
2. ** Control information**: read or write (through control bus);
3. ** Data message**: content read/written (transmitted via data bus).

1.8 Address bus

• ** Address bus width** determines ** address ability of CPU**: N root address line → addressable $2^N$ A storage unit.
• 8086 20 address bus $2^{20}$ = 1 MB memory space.

1.9 Data bus

• ** Data bus width** determines how much data is transmitted at one time** (bit numbers).
• 8086 Data bus **16 ** 2 byte; 8088 only 8 by 1 byte.

1.10 Control bus

• ** Control bus** is a collection of ** some different control lines** and each single line expresses a control message.
• Direction cannot be generalized: some are sent by CPU (e.g. “read” signals) or others by external chips to CPU (e.g. interrupt the request line).

** Calculating Example**: address bus width is 20, memory address space size = $2^{20}\ \text{B} = 1048576\ \text{B} = 1\ \text{MB}$。

1.11 Memory address space (overview)

• In each PC, the size of the memory address space is limited by the width of the address bus; the CPU locates it uniformly.

1.12 Main Board

• The main plate contains cores connected through the bus: CPU, storage (RAM), peripheral chips (interface cards), extended slots.

1.13 Interface cards

• CPU cannot directly control external settings (showers, keyboards, soundboxes), but is indirectly controlled by issuing orders to ** repositories (ports)** on interface cards.
• CPU sends a command to the interface card via the bus, which controls the external work as ordered.

1.14 Storage chips of all types

| Classifications Characteristics Example |------|------|------| | Random memory RAM | readable, blackout lost | primary, visible | | Read-only memory ROM | read only, power is cut | BIOS ROM (with an opener) |

1.15 Memory address space

• ** Memory address space**: CPU views various types of storage as a ** Logical repository consisting of several storage units**, with each physical repository having an address space in the address space.
• 8086 PC address space allocation (from low to high): main repository address space → visible address space → various ROM address space. ** The reading and writing of an address is actually the reading and writing of the physical memory to which it belongs. **

2. Depositors

2.1 General repository

8086 CPU has 14 senders (16 bits accessible): AX, BX, CX, DX, SI, DI, SP, BP, CS, DS, SS, ES, IP, FLAGS. Of these, 4 are common repositories, usually used to store general data:

| 16-bit repository 8-bit low 8-bit high |------------|---------|---------| | AX (cumulation) | BX (base) | CX (calculation) | DX(data)

• In order to ensure compatibility, eight of the previous CPUs can be used independently; eight and eight do not affect each other**.

2.2 Storage of words in repositories

• One word exists in a 16-bit repository: high byte, low byte.
• Example: AX = 01001110000B = 4E20H, AH = 4EH, AL = 20H.

2.3 Several compilation instructions

mov ax, 18      ; ax = 18
mov ah, 78      ; ah = 78（不影响 AL）
add ax, 8       ; ax = ax + 8
mov ax, bx      ; ax = bx
add ax, bx      ; ax = ax + bx

• Commands to operate** with two operational object digits**.
• Directly discard ** (high) bits when the archive width is exceeded**:mov al, 98H Back add al, 98H,98H+98H = 130H,8 bits are unattainable, and only 8 bits of 30H** is retained in **AL (at CF, see chapter 11).
• Insert 0 before the letter when hexadecimal in the compilation 0C0H) or the compiler will use it as a symbol.

2.4 Physical address

• 8086 There is a 20-bit address bus (location 1MB), but the CPU is an internal 16-bit structure - a 16-bit address cannot give 20-bit addresses directly, so ** 2 16-bit synthetic physical addresses** are required.

2.5 CPU with 16-bit structure

• 16 bit structure: Operator handles up to 16 bit data at a time, register has a maximum width of 16 bits, and route between repository and operator is 16 bit.

2.6 Method of giving physical address by 8086 CPU

$$\textbf{物理地址} = \textbf{段地址} \times 16 + \textbf{偏移地址}$$

• x16 In binary, i.e. ** left 4 bit** (hexadecimal 1 bit left, followed by 0).
• Example: Sector address 123CH, offset address 0008H → Physical address = 123C0H + 0008H = 123C8H.

2.7 The essence of “part address x 16+ offset address = physical address”

• The CPU gives the physical address of the memory unit by “basic address (part address x 16) + offset address relative to base address”.
• Two 16-bit addresses (part, offset) synthesized a 20-bit physical address.

2.8 Concept of paragraph

• ** “Paragraph” is not really divided into memory**, but rather a logical concept resulting from the CPU sub-location approach; a number of “paragraphs” can be arranged as needed.
• The starting address of a segment (paragraph address x 16) must be 16 multiple.
• Offset address 16 bits a maximum of 64 KB$2^{16}$）。
• The same physical address can be obtained by a combination of “part addresses: offset addresses” such as 21F60H = 2000H: 1F60H = 21F6H:000H .

2.9 Segment Depositary

• 4 Sector senders: CS, DS, SS, ES.
• 8086 Positioning instructions or data should be used at all times using the “Step Address: Offset Address”; a sector address is stored in a sector register.

2.10 CS and IP

• ** CS (Code Segment Depositary) + IP (Directive Pointer Depositary)**: Instructions CPU to currently read command addresses.
• ** At any moment, the CPU uses the CS:IP pointers as instructions**:
  1. Read commands from CS x 16+IP and send them into command buffers;
  2. IP = IP + length of command read (to the next command);
  3. Execute the directive, step 1.
• 8086 After power is activated or restored: CS = H, IP = 000000H, i.e. starting from 0H unit - which is the first command of the BIOS ROM.

2.11 Directives to modify CS, IP

• 8086 Most repositories can be modified with mov, but mov cannot be used to set up CS, IP.
• The commands that can modify CS and IP are collectively referred to as** transfer instructions**, the simplest being jmp：

jmp 2AE3:3        ; 同时修改：CS=2AE3H, IP=0003H（段间转移）
jmp ax            ; 仅修改 IP = ax（段内转移，功能上类比 mov ip, ax）

2.12 Code segment

• Treats a memory as a code segment, simply placing its segment address on CS, and the deviation of the first command on IP, and CPU executes the instructions accordingly.
• ** The code segments are artificial; CPU only recognizes CS:IP .**

Experiment 1 View CPU and memory, program with machine commands and compile commands

Directly handle CPU and memory with Debug, commonly used commands:

| Command, cyborg, function, cyborg. |------|------| | R | View/modify the contents of the register (R ax Change AX) | D | View memory content (D 段地址:偏移） | | E | Rewrite MemoryE 1000:0 41 42 43） | | U Translation of memory machine commands into compilation commands (inverse compilation) | A Writing machine commands to memory in compilation command format | T Implementation of a directive (one-step tracking) | G | Execute to Specified Location (G 0016） | | P | Execute until cycle end/interrupt return (intra-interrupt internal when encountered with int command) | | Q Quit Debug

3. Depositors (RAM access)

3.1 Storage of memory words

• ** Small-end approach (low-to-low, high-to-high): the word ** low-bytes are stored in the low-end unit and the high-bytes in the high-end unit.
• Example: If 4E20H is stored in a unit from 2000H, then (20000H) = 20H, (20001H) = 4EH; 20000H, 20001H together form a unit with a value of 4E20H.
• Team: consisting of two consecutive memory units starting with low address units.

3.2 DS and [address]

• ** DS sector address usually stored to access data**;[address] is a memory unit with an address offset to Adress and a sector address is defaulted to DS.

mov bx, 1000H
mov ds, bx       ; 注意！8086 不支持 mov ds, 立即数，必须经通用寄存器中转
mov al, [0]      ; al = (DS×16+0) 中的字节
mov [0], al      ; 将 al 写入该内存单元

3.3 Transmission of words

• The transmission of words is completed once (16 data lines work simultaneously):mov ax, [0] One reading of 0, 1 of 2 units, 8 bits from high address units and 8 bits from low address units.

3.4 mov, add, sub

| Form of instruction |----------|------| | mov/add/sub repository, data| add ax, 8 | | mov/add/sub repository, register mov ax, bx | | mov/add/sub repository, memory unit mov ax, [0] | | mov/add/sub memory unit, register add [0], ax | | mov sector register, register mov ds, bx | | mov repository, segment register mov ax, cs |

** Can’t**:

• mov ds, 1000H: A sector register cannot be given directly to an immediate number and must be passed through the universal register;
• dd/sub is not capable of operating segment repositories;
• Not directly mov/add/sub between two memory units;
• ** The immediate number cannot be used as the intended number of operations** mov 8, ax）。

3.5 Data bands

Use a memory as a data section: insert a paragraph address into DS, use [偏移] Access to the module is sufficient. Data segments are also artificial.

3.6 Inn

• ** Bark**: a later-in-out (LIFO) structure, 8086 provides the relevant instructions with ** memory space** as anchor.

3.7 The stacking mechanism provided by CPU

• SS:SP indicator top element: SS storage segment address, SP storage offset address.
• ** The entry/exit of 8086 is in 2 bytes**.

push ax execution:

1. SP = SP − 2 (top pointer moved first to low address);
2. Sends ax content to a font to which SS:SP points.

pop ax execution:

1. Send the SS:SP-directed font data to ax;
2. SP = SP + 2。

• ** At the space warehouse**, SP points to the next module at the bottom of the stack (the maximum address unit of the stack space)**.
• Trench growth direction:** from high to low address**.

mov ax, 1000H
mov ss, ax
mov sp, 0010H    ; 栈空间 1000:0000~000FH（16 字节），空栈时 SP=0010H 指向栈底下一单元
push ax          ; 入栈
pop bx           ; 出栈

** Process exercise** (stamp space 1000: 000 000 000 FH, initial SP=0010H):

mov ax, 0123H
mov bx, 2266H
mov cx, 1122H
push ax          ; SP=000EH，(1000:000EH)=0123H
push bx          ; SP=000CH，(1000:000CH)=2266H
push cx          ; SP=000AH，(1000:000AH)=1122H
pop ax           ; ax=1122H，SP=000CH
pop bx           ; bx=2266H，SP=000EH
pop cx           ; cx=0123H，SP=0010H

The order of exit is the opposite of that of entry: the values of ax, bx, cx are interchanged before and after entry.

3.8 The problem with the super-frontier of the inn

• Before push SP only minus 2 and after pop SP only add 2,8086 does not guarantee that the mooring will not cross the border and will not be misreported due to the ultra-frontier.
• The programmer must have his or her own concern about the scope of the cage and arrange for enough room for the stack.

3.9 Push, Pop Command

Operatable object: depositor, segment repository, memory module.

push ax        ; 寄存器
push ds        ; 段寄存器
push [0]       ; 内存字单元
pop  [2]       ; 出栈到内存

3.10 Inn sections

• ** Bank**: Use a memory as a bank, just SS:SP points to it.

Experiment 2 programming with machine commands and compilation commands

• Use in Debug A Command writing compiles commands, learns how to read and write the stack mechanism and the register, memory.

4. First procedure

4.1 Process of a source program from writing to implementation

** Prepared (.asm) → Compiled masm (.obj)→ Connection link (.exe)→ Loading **

• Compiled: Translation of compilation instructions into machine code to generate target file.obj; also generate list file.lst.
• Connection: To assemble the target file as an executable.exe; also to generate an image file.map.

4.2 Source procedure

assume cs:codesg      ; 将代码段 codesg 与段寄存器 CS 关联（假设性说明）

codesg segment        ; 定义一个段的开始
    mov ax, 0123H
    mov bx, 0456H
    add ax, bx
    add ax, ax

    mov ax, 4c00H     ; 程序返回：AH=4CH（功能号），AL=00H（返回码）
    int 21H           ; 调用 DOS 中断完成返回
codesg ends           ; 段结束

end                   ; 程序结束标记（编译器遇 end 结束编译）

| Fake commands. |--------|------| | xxx segment / xxx ends | Define a section (in pairs) | end Mark the end of the whole program (converter ends) | assume “Assumption” is linked to a certain repository.

** Two “ends” are not the same thing **:

• end Yes** End of procedure**: notify the compiler during the compilation period that the “source process is over”;

• mov ax,4c00H + int 21H Yes** The procedure returns**: the CPU control is returned to the system during operation. Without it, the program will continue to run into the back memory after implementation.

• ** Mark: ** codeg as a paragraph name was eventually compiled and processed as a sector address.

4.3 Edit Source Program

• Creates the .asm source file (pure text, without format) with a text editor.

4.4 Compilation

• Compile source files with a compiler (masm): Generate target file .obj (and optional list file .lst).

4.5 Connections

• Connect the target file with a connector (link): Generate an executable.exe (and an optional image file.map). When the program is large, it can be compiled and reconnected into multiple source files and can call the library file.

4.6 Compiled and connected in a simplified manner

• Direct return to the compiler and connect interactive queries can skip the middle file generation (simplified mode).

4.7 Implementation of 1.exe

• Enter the executing file name directly in DOS.comand.com to load it into memory and execute it.

4.8 Who loads the program in the enforceable document into the memory and makes it operational?

• Command.com (shell program for DOS) loads .exe into memory: finds a sufficient volume of free memory → Creates **PSP (Procedure segment prefix, 256 bytes) ** Loads after PSP.
• After loading: Deposit address of PSP in DS (started by 256 bytes after PSP, i.e. address of the segment = DS+10H), CS:IP point to the program entry, SS:SP point to the top of the stack.

4.9 Tracking of process implementation

• Debug entered .exe as parameter and then tracked: T Article by article, encounter int 21H Use P Normal end of return.

Experiment 3 Programming, compiling, connecting, tracking

• Walk the whole “Prepar source → masm compile → link connection → Debug track” process.

5. [BX] and Loop Directives

5.1 [BX]

• [bx] is the memory unit with the offset address in bx and the default DS address.

mov bx, 0
mov ax, [bx]      ; 等价于 mov ax, (DS:0)
inc bx            ; bx = bx + 1

• inc 寄存器Add 1;dec 寄存器: minus 1 (the two instructions are often followed by moving points).

5.2 Loop Directive

• CPU Implementation loop 标号：
  1. (cx) = (cx) − 1；
  2. cx: ** Not 0, transferred to mark**; 0, down.
• ** Number of storage cycles** in cx.

** Classic example: calculation $2^{12}$(no multiplier)**

    mov ax, 2
    mov cx, 11         ; 循环 11 次，每次翻倍
s:  add ax, ax         ; ax = ax × 2
    loop s             ; cx-- ≠0 就跳到 s

Implementation result: AX = $2^{12}$ = 4096 = 1000H。

5.3 Tracking loops performed with loop commands in Debug

• Use G 偏移 Directly execute outside cycle (jumping cycle), avoid T Article by article 12; or P After one execution loop.

5.4 Differing treatment of instructions by Debug and compiler masm

Use idata for offset address in the source application, prefix to visible writing ds:[0]。

5.5 Joint application of loop and [bx]

Typical setup: add a continuous memory (ffff: 0 ~ffff:b ) to sum 12 bytes to dx):

    mov ax, 0ffffH
    mov ds, ax
    mov bx, 0          ; 偏移指针，从 0 单元开始
    mov dx, 0          ; 累加结果
    mov cx, 12         ; 12 个单元
s:  mov al, [bx]
    mov ah, 0          ; 字节扩展为字，避免 add dx, ax 时误带高位
    add dx, ax
    inc bx
    loop s

5.6 Prefix

• ** Prefix**: visible given paragraph address, if ds:[bx]、cs:[bx]、ss:[bx]、es:[bx]。
• appears in the command that accesses the memory module, which specifies the selected part of the memory unit.

5.7 A safe space

• In the general PC machine, 0:200H ~0:2FFH ’s 256 bytes is free ** and is directly usable by the Debug experiment; do not write data randomly to unknown memory.

5.8 Use of prefixes

• Use prefix to access when you place the data in another section (e.g. code, stack); default DS when no prefix.

Use of experiment 4 [bx] and loop

• Complete access to continuous memory units (e.g., adding, copying) with loop and [bx].

Procedures with multiple paragraphs

6.1 Use of data in code segments

• When the data defined in the program is at the top of the code, let CS:IP skip the data, use it end 标号 Designation** of programme entrance**:

assume cs:code
code segment
    dw 0123H,0456H,0789H,0abcH,0defH,0fedH,0cbaH,0987H   ; define word，8 个字数据
start:                        ; 程序入口标号
    mov bx, 0
    mov ax, 0
    mov cx, 8
s:  add ax, cs:[bx]           ; 数据在代码段，用 cs 段前缀访问
    add bx, 2
    loop s

    mov ax, 4c00H
    int 21H
code ends
end start                     ; end 后标号指示程序从 start 开始执行

Implementation result: AX = sum of 8 words = 4 BDBH.

• dw(definine word) Defines font data;db(define byte) defines byte data.

6.2 Use of stacks in code

Use dw In this section, open a canal and point SS:SP at it:

    dw 0,0,0,0,0,0,0,0     ; 8 个字作为栈空间，占 16 字节
start:
    mov ax, cs
    mov ss, ax
    mov sp, 10H            ; 空栈 SP 指向栈底（最高单元）下一单元（16）

6.3 Place data, codes, stacks in different segments

• A section capacity 64KB with data/codes/stamps confusing; multiple paragraphs can be defined:

assume cs:code, ds:data, ss:stack
data segment
    dw 0123H, 0456H
data ends
stack segment
    dw 0,0,0,0,0,0,0,0
stack ends
code segment
start:
    mov ax, stack
    mov ss, ax
    mov sp, 16
    mov ax, data
    mov ds, ax           ; 访问 data 段前，先把段地址送 DS
    ; ...业务指令...
    mov ax, 4c00H
    int 21H
code ends
end start

Key:assume Just “Assumption” for the compiler, CPU does not automatically send a section address into DS/SS,** which must be set by command; only CS:IP is based on the loading program end 入口标号 Automatic settings.

Experiment 5 Develops and debugs multi-part programs

• Develops and debugs procedures that contain data segments, stacks, code segments.

7. More flexible methods for locating memory addresses

7.1 and or instructions

• and: in place and (two-one-one-one), often used to clear designated places**;
• or: in place or (one and one), often used to place the assigned place** in 1**.

mov al, 01100011B
and al, 11011111B   ; 第 5 位清零，其余不变 → 01000011B
or  al, 00100000B   ; 第 5 位置 1，其余不变

7.2 About ASCII Codes

• ASCII code difference of the same letter 20H, with a difference of only ** 5 (from 0)**.

7.3 Data in Character

• Quote character constants in source program:db 'unIX' Equivalent db 75H,6EH,49H,58H。

7.4 Case conversion problems

• ** Upper case ** lower case**: position 51 (or xx, 00100000B）；
• ** lowercase ** uppercase**: 5th Zeroand xx, 11011111B）。

Applies: converting the string ‘BaSiC’ in Data to uppercase, ‘minIX’ to lowercase:

assume cs:code, ds:data
data segment
    db 'BaSiC'
    db 'MinIX'
data ends
code segment
start:  mov ax, data
        mov ds, ax
        mov bx, 0
        mov cx, 5
s:      mov al, [bx]          ; 第一个字符串 (偏移 0~4)
        and al, 11011111B     ; 转大写
        mov [bx], al
        mov al, [bx+5]        ; 第二个字符串 (偏移 5~9)
        or  al, 00100000B     ; 转小写
        mov [bx+5], al
        inc bx
        loop s
        mov ax, 4c00H
        int 21H
code ends
end start

7.5 [bx+idata]

mov ax, [bx+200]      ; 偏移地址 = (bx)+200，等价写法：
mov ax, 200[bx]
mov ax, [bx].200

7.6 Treatment of arrays by [bx+idata]

• Two arrays from [bx] and [bx+idata] Starts with the same bx synchronized positioning (e.g. example 7.4 above).

7.7 SI and DI

• SI (source changer), DI (purpose changer): function close to bx, but ** cannot be dismantled to two 8-bit repository**.

mov si, 0
mov ax, [si]
mov di, 0
mov ax, [di+10]

7.8 [bx+si] and [bx+di]

• The deviation is expressed in two variable/base repositorys:mov ax, [bx+si] = mov ax, [bx][si]。

7.9 [bx+si+idata] and [bx+di+idata]

• Offset = base + variable + constant:mov ax, [bx+si+idata]。

7.10 Flexible application of different approaches to address

• 8086 to use [...] Only bx, bp, si, di (and bx/bp does not appear simultaneously, s/di does not appear simultaneously):

| Form Name Example |------|------|------| | [idata] Direct location [0] | | [bx] | Depositor’s indirect address [bx] | | [bx+idata] Repository relative address [bx+8] | | [bx+si] | Base site change of address [bx+si] | | [bx+si+idata] Change of address relative to base [bx+si+8] |

• Correct combination: bx/si, bx/di, bp/si, bp/di;** error combination**:[bx+bp]、[si+di]。
• ** Default paragraph rule**: Default paragraph repository ** SS** when bp appears in address; remaining default DS. Available prefix changes.

Experiment 6 Procedures in practical courses

• Integrated exercise on the location of this chapter.

Experiment 7 Site approach applications in structured data access

• Access to structured data using multiple addresses (e.g., employee information sheets: multiple fields per entry, location by base + change of address).

8. Two basic data-processing issues

8.1 bx, si, di and bp

• Of 8086 available [...] The repository: bx, bp, si, di; bx/bp is “base” and si/di is “changed”.
• bp default match with SS, the rest default with DS.

8.2 Where are the data processed by the machine command?

Data processed by the machine command can be stored in three places: Intra-Directive (immediate number)2 repository 3 (part address SA: offset address EA).

8.3 Expression of data location in the compilation language

| Location, expression, exemplification. |------|------|------| | Count right now the idata gill, written directly in the command. mov ax, 1 | | Storer? mov ax, bx | | Sector Address + Offset mov ax, [0] |

• The immediate number can only be used as a source number and not as an end.

8.4 Approach to address

8.5 Length of data to be processed by the Directive

8086 can handle byte (8 bit) and word (16 bit) dimensions as indicated below:

1. ** Repository name specified**:mov ax, [0] It’s a word operation.mov al, [0] is byte operation.
2. **The operator word ptr / byte ptr indicates:

mov word ptr [bx], 0    ; 向 [bx]、[bx+1] 组成的字单元送 0
mov byte ptr [bx], 0    ; 只向 [bx] 字节单元送 0

3. Other ways: e. g. push/pop default only word operations.

8.6 Integrated application of address-seeking approaches

• The same problem can be achieved by different approaches to location (e.g. direct location and relative location rewrites the same access) to the applicable scenarios.

8.7 div command

• Division: 8 or 16 bits in register or memory (** cannot be immediately **).
• ** By default divided in AX (8 bits) or DX and AX (16 bits divided, DX 16 bits higher)**.

| Distinction of width, dichotomy, dichotomy. |----------|--------|----|------| | 8 bits AX ** AL** AH** | 16 bits ** DX (high): AX (low)** ** AX** ** AX** ** DX** |

; 8 位除法：1001 / 100
mov ax, 1001
mov bl, 100
div bl              ; AL = 商(10 = 0AH), AH = 余(1)

; 16 位除法：100001 / 100
mov dx, 1
mov ax, 86A1H       ; DX:AX = 186A1H = 100001
mov bx, 100
div bx              ; AX = 商(03E8H = 1000), DX = 余(1)

** Deduction spill**: CPU produces ** excretion, triggers ** break** (see chapter 12 for more details) if the carrier exceeds the storage capacity (8 defamers > 255, 16 defamers > 65535). The program is programmed in such a way as to ensure that it can be put down.

8.8 Hypothetical instructiondd

• db Define bytes,dw Definitions,dd Define two words (dword, 4 bytes):

dd 12345678H        ; 占 4 字节

8.9 dup

• dup used to repeat definition data:

db 3 dup (0)            ; 等价 db 0,0,0
db 3 dup (0,1,2)        ; 等价 db 0,1,2,0,1,2,0,1,2
db 200 dup (?)          ; 预留 200 个字节的空间（不确定值）

9. Rationale for transfer orders

9.1 Operator offset

• offset 标号 Number obtained** offset address** (processed by compiler):

start: mov ax, offset start    ; ax = start 处的偏移地址

9.2 Jmp Directive

• jmp is** Unconditional transfer instructions**: only IP can be modified, or CS and IP can be modified simultaneously.

9.3 Jmp Directive for Transfer Based on Location

jmp short 标号      ; 段内短转移：IP = IP + 8 位位移；范围 −128 ~ 127
jmp near ptr 标号   ; 段内近转移：IP = IP + 16 位位移；范围 −32768 ~ 32767

• The machine code** does not contain the address of the moving purpose, but contains the offset relative to the current IP**:** offset = mark offset - offset of the first command after jmp command** to facilitate floating assembly in the memory of the program.

9.4 Jmp Directive for the purpose of the transfer

• Inter-part transfer (far, far transfer): The machine code contains the address of the purpose segment and the deviation address.

jmp far ptr 标号    ; CS = 标号所在段地址，IP = 标号偏移地址

9.5 jmp command for transfer address in repository

jmp ax              ; IP = ax（不改变 CS）

9.6 jmp command in transfer address memory

jmp word ptr [bx]       ; 段内：从内存字单元取偏移送 IP
jmp dword ptr [bx]      ; 段间：低字 → IP，高字 → CS

9.7 jcz Directive

• jcz = jump if cx is zero: cx is 0, otherwise execute down (short transfer in paragraph, shift -128 ~127).

jcxz 标号        ; 等价于：if ((cx)==0) jmp short 标号

9.8 Loop Directive

• loop 标号: cx minus 1, cx≠0 is transferred; also ** Short transfer within paragraph**, 8 bit shift in machine code.

9.9 Meaning of transfer based on place transfer

• The “relative shift” rather than an absolute address is recorded in the transfer order, and the program is loaded to any location of the memory and can be executed correctly.

9.10 Compilers ’ detection of diversions

• The compiler detects transferovers, which are directly compiled errors (e.g. jmp short moves in excess of −128 ~127).

Experiment 8, analyze a strange program.

• Following an “unusual” program to understand the code of the shift.

Experiment 9 programming by material

• Practice transfer instructions by programming the given material.

10. CALL and RET directives

10.1 ret and retf

10.2 Call Directive

• CPU execution of the call ** Reverts back to the address (current IP or CS:IP ) and then transfers **.

10.3 Call Directive to transfer according to place

• call 标号(near): Push IP; jmp near ptr mark (16-bit shift).

10.4 The purpose of the transfer is addressed in the Call Directive

• call far ptr 标号(apogee): push CS; push IP; jmp far ptr.
• In the middle of the call, press CS, press IP, which corresponds to retf.

10.5 Call command for transfer address in repository

• call reg: push IP; jmp reg (IP = 16-bit repository).

10.6 Call command in transfer address memory

• call word ptr 内存:push IP; jmp word ptr memory unit.
• call dword ptr 内存:push CS; push IP; jmp dword ptr memory unit.

10.7 Co-use of call and ret

    ; 主程序
    mov ax, 0
    call s          ; 调用子程序 s：push 返回地址后跳转
    mov bx, ax      ; 返回后继续
    mov ax, 4c00H
    int 21H

s:  add ax, 1       ; 子程序
    ret             ; 返回：pop IP 回到 call 的下一条指令

10.8 Mul Directive

• mul can only be used as ** repository or memory unit** (not immediately).

| Multiplier numeric numeric numeric numeric graphs |----------|--------|------|------| | 8 bits | 16 bits | | r16/ m16 ** DX (16 bit high): AX (16 bit low)** **

mov al, 64
mov bl, 64
mul bl          ; AX = 64×64 = 4096 = 1000H

mov ax, 100
mov bx, 100
mul bx          ; DX:AX = 100×100 = 10000 = 2710H（DX=0, AX=2710H）

10.9 Modularized program design

• Sub-procedure (process) = a functional segment to call, ret back and avoid repetition of the code.

10.10 Question of parameters and transmission of results

• Sub-programs need to be passed on to the sub-program before they are called, and the sub-program needs to be returned to the main program — this is the question of the transmission of parameters and results.

10.11 Transmission of volume data

• When multiple parameters (volume data) are passed by ** memory unit (data table)**: Place the parameters in the memory area and send the address with ds:si / ds:bx .
• Three modes of communication:

| Modalities Applicable |------|------| | Repository transfer | less parameters | | Memory units (data tables) transfer multiple parameters (volume data) | (see note 4)

Backer transfer example: sub-cube calculates the three-verse of ax, resulting in dx:ax:

cube:   mov bx, ax
        mul bx          ; dx:ax = N × N
        mul bx          ; dx:ax = N² × N = N³
        ret

10.12 Problems with depository conflicts

• The repository used in the sub-procedure may be in conflict with the main program in use (e.g., the master program uses bx as a pointer, and cube changes bx).
• Standard solution framework: sub-process starts with all of the repositories used and returns to the front stacks (note the reverse order):

sub:    push ax             ; 保存现场
        push bx
        push cx
        ; ... 子程序功能，随意使用 ax/bx/cx ...
        pop cx              ; 恢复现场（逆序）
        pop bx
        pop ax
        ret

Experiment 10 Write Subprogram

• Writes multiple sub-programs with parameters and calls.

Course design1

• Organizes this chapter sub-programme into a comprehensive program (shows the function menu + multiple sub-apps).

11. Sign repository

The sign register (FLAGS) functions in place and each has a special meaning. 9 bits were used for the 16 bits of 8086 (also: the AF Auxiliary Bitmap is in the 4th place for BCD operations, and teaching materials are not developed; TF/IF is in the 8/9 place, see chapters 12, 15).

11.1 ZF logo

• ** ZF (6-bit) zero mark**: ZF = 1 at 0, otherwise ZF = 0.

mov ax, 1
sub ax, 1       ; 结果 0 → ZF=1

11.2 PF logo

• Perfect sign of PF (2nd place): PF = 1.

mov ax, 1
sub ax, 1       ; 结果 0，0 个 1（偶数）→ PF=1

11.3 SF logo

• ** SF (7 bit) symbol**: SF = 1, i.e. highest SF = result when the result is negative** (with symbol)**.
• ** SF counts only for symbol numbers**: SF indicators are positive and negative when results are numbered.

11.4 CF logo

• ** CF (bit 0) + sign**: ** Unsigned ** highest + / highest + debit → CF = 1.

mov al, 98H
add al, 98H     ; 98H+98H = 130H，8 位放不下 → CF=1，AL=30H

11.5 OF logos

• F (11th bit) spill mark:** with symbol** calculation results beyond what can be expressed by machine → OF=1.
• 8 bit with symbol range -128 ~127; 16 bit - 32768 ~ 32767.

** The difference between CF and OF**:

• ** CF and OF are not related and record results from different perspectives. **

11.6 Adc Directive

• adc ax, bx: ax = ax + bx + ** CF** (plus by bit).
• Use: Calculated in descending order to ** greater than the size of the register **, which results in a CF-to-high position.

; 16 位寄存器实现 32 位加法：1EF000H + 201000H = 3F0000H
mov ax, 001EH
mov bx, 0F000H
add bx, 1000H       ; 低 16 位相加：F000H+1000H = 0000H，CF=1
adc ax, 0020H       ; 高 16 位相加再加 CF：1EH+20H+1 = 3FH
                    ; 结果 AX(高)=003FH, BX(低)=0000H

11.7 Sbb Directive

• sbb ax, bx: ax = ax — bx — ** CF** (net of debits) for high-debit transmission by large number.

11.8 cmp Directive

• cmp ax, bx ax - bx calculation without saving results, only affecting sign repository for subsequent condition transfer instructions.

** Unsigned number compared results judgement**:

| cmp a, b post-relationship |-----------|------|------| | ZF=1 | a = b | — | | CF =1 | a < b | generating debit | | CF = 0 and ZF = 0 a > b |

** There is a comparison of symbol numbers**: see if SF is the same as OF (a>b ⇔ SF = OF and ZF = 0; a<b ⇔ SF ≠ OF).

11.9 Conditional Transfer Directives for Testing Comparative Results

Conditional transfer instructions are all short transfers within ** paragraph** (diversion − 128 ~ 127) and are usually followed closely by cmp.

| Instructions, meanings, judgmental conditions, equivalent orders, |------|------|----------|----------| | je | Equivalent transfer | ZF=1 jz | jne ZF=0 jnz | jb | Less than offset (unsigned) | CF = 1 | jnae/jc | | jnb | CF=0 jae/jnc | | ja | Higher than then transfer (unsigned) | CF = 0 and ZF = 0 | jnbe | | jna | CF = 1 or ZF = 1 | jbe | | jl | | ≠ ≠ | | ng ng | | | | ≠ ≠ ≠ ≠ ≠ ≠ ≠ ≠ ≠ ≠ ≠ ≠ ≠ ≠ ≠ ≠ ≠ ≠ ≠ ≠ ≠ ≠ ≠ ≠ ≠ ≠ ≠ ≠ ≠ ≠ ≠ ≠ ≠ ≠ ≠ ≠ ≠ ≠ ≠ ≠ ≠ ≠ ≠ ≠ ≠ ≠ ≠ ≠ ≠ ≠ ≠ ≠ ≠ ≠ ≠ ≠ ≠ ≠ ≠ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | jge SF = OF | jnl | | jg | | (signed) | SF = OF and ZF = 0 | jnle | | jle | less than equal to transfer | SF≠OF or ZF=1 ng |

Memory: equal equal; below/abve with no symbol height; less/greater with symbol size; n = not. Other js/jns(Push SF)jp/jnp(by PF).

cmp ax, bx
je  equal       ; ax==bx 才跳
; ...
equal:

11.10 DF symbols and string transport instructions

• ** DF determines the direction of the increase or decrease in the repository after the string operation**:
  • cldDF = 0,** incremental**;stdDF = 1,** minus **.

| Command, call, move, call. |------|------| | movsb | Bytes: es: [di] = ds: [si]; si, di ±1 | | movsw | Delivery by word: es: [di] = ds: [si]; si, di ±2 | | rep movsb Duplicate movsb (cx times)| according to xx

    mov ax, data
    mov ds, ax
    mov ax, dest
    mov es, ax          ; 目的段用 ES
    mov si, 0
    mov di, 0
    mov cx, 8
    cld                 ; 递增方向
    rep movsb           ; 连续传送 8 个字节

11.11 Pushf and Popf

• pushf(i) Staples of sign depositors;popf: Eject from the stack into the sign repository.
• Cooperates with the temporary storage and setting of the sign register.

11.12 Representation of the mark register in Debug

| Marker = 1 = 0 | |------|----|----| | OF | OV | NV | | DF | DN | UP | | IF | EI | DI | | SF | NG | PL | | ZF | ZR | NZ | | PF | PE | PO | | CF | CY | NC |

Experiment 11 Write Sub-Procedure

• Comprehensive exercise sub-program and marking position judgement.

12. Internal interruption

12.1 Generation of internal interruptions

The internal interruption occurs when:

12.2 Interruption of processing procedures

• ** Interrupted processing (interrupted routines)**: CPU received information about the interruption and transferred to the process for execution.

12.3 Interrupted vector schedule

• ** Interrupted vector chart**: create a map of the “Interrupt type code → Interrupted processing program entry address”.
  • Interrupted vector table for 8086 000: 000 000 ~ 000: 03FF, ** 1024 bytes**;
  • For each table item 4 bytes: low-word offset IP, high-word field address CS;
  • Interruption of type N with entry addresses at 0: Nx4 (IP) and 0: Nx4+2 (CS).

Example: Interrupted by type code 9 (keypad) with vector at 0:9x4 = 0:24H .

12.4 Interruption of process

CPU hardware automatically complete (interrupted process):

1. Obtaining break type N;
2. ** pushf** (marked repository);
3. TF = 0, IF = 0 (not responding to one-step interruption, shielded out interruption during interruption);
4. push CS、push IP；
5. (IP) = (N×4)，(CS) = (N×4+2) — Transferred to perform interrupted routines.

12.5 Interruption of processing procedures and iret directives

At the end of the break routine, return with iet at the equivalent of:pop IP → pop CS → popf, which corresponds to the pressure of the interrupted process.

** Interrupted standard structure**:

doit:   push ax             ; 保护现场
        ; ... 处理 ...
        pop ax              ; 恢复现场
        iret                ; 中断返回

12.6 Disruption treatment

• The CPU produces a 0-cut interruption when the partition spills; the default 0-cut processing program shows “Divide overflow” and returns to DOS.

12.7 Programming processing 0 interrupted

• Complete route: 1 to prepare cut-off routines do0 →2** Installation**: copying do0 to memory (0:200 H) that is not covered (0:200 H)** sets the break vector table**: change 0 to 0:200 H.

12.8 Installation

• Copy the normal machine code from the code segment** to the secure memory (0:200H ) with movsb and save the original entrance to the vector table.

12.9 do0

; do0 例程：显示 "divide error!" 后结束程序
do0:    jmp short do0start
        db "divide error!"          ; 字符串放在 0:202H 处
do0start:
        mov ax, cs
        mov ds, ax
        mov si, 202H                ; 指向字符串（安装后 cs=0，偏移不变）
        mov ax, 0b800H              ; 显存段
        mov es, ax
        mov di, 12*160+36*2         ; 第 12 行第 36 列
        mov cx, 13                  ; 13 个字符
s:      mov al, [si]
        mov es:[di], al             ; 写字符
        mov al, 2                   ; 颜色（绿色）
        mov es:[di+1], al           ; 写属性
        inc si
        add di, 2
        loop s
        mov ax, 4c00H               ; 例程功能是"报错后结束程序"，故用 4c00H 返回
        int 21H

Note: do0 end with mov ax,4c00H; int 21H ** The closure of the proceedings** rather than the iet — the process should be discontinued once the process has been completed, as the exclusions indicate that the process cannot continue. If the normal process is completed and ** returns to the original application for continued operation**, use ET.

12.10 Set the break vector

; 设置 0 号中断向量：0:0 = 200H，0:2 = 0
mov ax, 0
mov es, ax
mov word ptr es:[0], 200H
mov word ptr es:[2], 0

12.11 One Step Break

• TF=1, CPU triggers a one-step break for each instruction type 1 and Debug uses it to achieve one-step tracking.
• Automatically set TF to 0 during the break to avoid interrupting the routine itself; pushf saved the original TF before entering the routine.

12.12 Special cases of response interruption

• In some cases (e.g. setting up SP immediately after setting the SS command), CPU will not respond between the two instructions to ensure that SS:SP is set in pairs.

Experiment 12, prepare an aborted process for 0.

• Complete realization: Creates a do0 → installation setting vector Quantities triggers validation with detachment spills.

13. Int Directives

13.1 Int Directives

• int n The trigger type code n is interrupted and the execution process is equal to: n → pushf → TF=0, IF=0 → push CS, push IP → read nx4 tabs jump.
• Int command allows programmers ** to call the interruption routine offered by the system at their own initiative**; Iret returns at the end of the routine.

13.2 Disruption routines for applications to be called

The process of preparing and installing the break schedule is the same as the break number 0: write the break schedule and install it to a secure memory (0:200H ).

** Example: Write and install 7ch interrupted routines with the function of calculating the square of word data (parameter ax, result dx:ax )**:

; 例程本体
lp:     mul ax              ; dx:ax = ax × ax
        iret

; 安装：复制到 0:200H（略），设置 7ch 向量（7CH×4 = 1F0H）
        mov ax, 0
        mov es, ax
        mov word ptr es:[1F0H], 200H
        mov word ptr es:[1F2H], 0

; 调用
        mov ax, 3456
        int 7ch             ; 返回后 dx:ax = 3456 的平方

13.3 In-depth understanding of int, iret and inn

• int n and call The difference: all jumps after returning to the address, but the int presses the ** sign register + CS + IP totalling 3 words** (call 1 ~2 words) and the int clears TF, IF.
• iret and retf Distinction: Iret played more than once** sign repository** (pop IP → pop CS ** popf).
• Barn balance: The baryard exit that interrupts the regular entrance/exit must match to ensure that the iret pops up the right content.

13.4 Interruption routines provided by BIOS and DOS

• ** BIOS (basic input output system)**: a series of interruption routines were installed by the program in ROM on start-up; DOS was installed after start-up.
• Applications call on them to complete hardware-related operations without concern for hardware details.

13.5 Installation of BIOS and DOS Interrupted routines

• During the start-up process: After the CPU is powered, implement the BIOS Initialization Program → BIOS installs its own interruption routines (e.g. int 9, int 10H, int 13H) →BIOS leads DOS to start its own interruption routines (e.g. int 21H).

13.6 BIOS Interrupted routine application

int 10H (screen/show-related), with a specified function number by aah:

; 在屏幕第 5 行第 12 列显示一个黑底绿色的字符 '!'
mov ah, 2        ; 2 号功能：置光标位置
mov bh, 0        ; 第 0 页
mov dh, 5        ; 行
mov dl, 12       ; 列
int 10H

mov ah, 9        ; 9 号功能：在光标位置显示字符
mov al, '!'
mov bl, 2        ; 颜色属性（绿色）
mov bh, 0
mov cx, 1        ; 显示次数
int 10H

13.7 DOS Interruption routine application

int 21H (procedural function):

| Oh, my God. |----|------| | 4CH | program returns (mov ax,4c00H + int 21H） | | 02H | Displays a character (dl = character) | | 09H | Show string ending ’$’ (ds:dx pointed to the string) | | 01H | Read a keyboard input and replay it, waiting to have a key (result in al) | | 07H | Read a keyboard input** do not return** (result in al) | | 0AH zirconium Read a string to the buffer zone

Buffer format for function 0AH (ds:dx points to buffer zone):

• 1 byte: maximum number of characters that can be accommodated in the buffer zone (prefilled);
• Bytes 2:** Number of characters actually read** (DOS completed on return, excluding return vehicles);
• 3 byte: Readed string (to end with a back car).

; int 21h 9 号功能显示字符串
assume cs:code
data segment
    str db 'Hello, Assembly!', '$'    ; 必须以 $ 结束
data ends
code segment
start:
    mov ax, data
    mov ds, ax
    mov dx, offset str
    mov ah, 9
    int 21h
    mov ax, 4c00h
    int 21h
code ends
end start

Experiment 13 Preparation, application of interrupted routines

• Custom int 7ch to interrupt and call.

Course design2

• Integrated application: multifunctional integrated process with interrupted routines.

Port

14.1 Reading and writing of ports

• The repository of various external/interface cards is known as port, and CPU accesss via port address unified site (independent of memory address space).
• Access ports have only two instructions: in (read)/out (write).

in  al, 60H        ; 从 60H 端口读一个字节到 al
out 20H, al        ; 把 al 写入 20H 端口

• Port address 0~FFH may be written directly in the command; more than FPH (range 0~H) must be placed first in dx:

mov dx, 3F8H
in  al, dx
out dx, al

14.2 CCOS RAM chip

• CMOS RAM consists of a real-time clock and 128-bytes RAM, powered by batteries, and continues to walk after off.
• CPU access through ** two ports**:
  • 70H (Address Port): Write the address of the CMOS unit to access;
  • 71H (data port): Read and write the content of the module.

mov al, 0
out 70H, al        ; 选中 0 号单元（秒）
in  al, 71H        ; 读出秒

14.3 shl and shr instructions

• shl (logical left): each move X bit left, minus 0,** the last move to CF**; the number can only be 1 or cl.
• shr (logical right): Move right, top 0, move to CF.

mov al, 01001000B
shl al, 1        ; 左移 1 位 = ×2 → 10010000B，CF=0
mov cl, 4
shr al, cl       ; 右移 4 位 → 00001001B（常用于取 BCD 高 4 位的十位）

• Moves one to the left equal to x 2, and one to the right equal to ÷2 (no symbol).

14.4 Time information stored in CCOS RAM

• The CMOS medium time information is stored at BCD code (two decimal places per byte, four ten places high, four places low).

| Unit, content, content, content, content. |------|------|------|------| | 0 seconds, 7 days, | 2 minutes 8 months | 4 years

• BCD value to ASCII display: ten bits = 4 bits high (4 bits to the right) + 30 H bits = 4 bits lowand 0FH）+30H。

Experiment 14 Access CCOS RAM

• Reads the time in CCOS and shows it.

15. External disruption

15.1 Interface chips and ports

• CPUs communicate with the outside through the port provided by the interface chip; the interface chip transmits information to the external/CPU and generates requests for interruption.

15.2 Interrupt information

Upon arrival of the external input/output, the chip is sent to the CPU** without interruption. There are two categories:

The interruption that is shielded is consistent with the internal interruption (IF will be set up when the interruption is in progress).

15.3 Processing of PC keyboards

1. Keyboard 60H port ** (circular is the scan code generated by the press, break code = code + 80H**, when released) to generate scanning codes for interface chips on the main panel;
2. Blockable interruption of interface chips to CPU ** Type 9 **;
3. CPU if IF=1, execute int 9 interrupt routine:
   • Read the scan code from the 60H port;
   • Converting the scan code to ASCII code/status information and depositing it in ** keyboard buffer zone**;
   • After processing, send the abort command to 20H port EOI (value 20H):

mov al, 20H
out 20H, al       ; 向外设中断控制器发送 EOI

15.4 Preparation of int 9 interruptions

Sets (for example, “Scan code display”):

1. ** Saves the original int9 portal** ( vector table 0:24H from 4 bytes) to secure memory (e. g. 0:200H );
2. Preparation of new routines: first call dword ptr Call original routine (which handles keys into the buffer zone and sends ** EOI**) and add a custom function;
3. Installing new routines to secure memory (e.g. 0:204H );
4. Replace 0:24H Table with the new routine entry.

15.5 Installation of a new int 9 interrupted routine

; 新 int 9 例程（已安装到 0:204H，故 cs=0；原入口保存在 0:200H）
newint9:
        push ax
        push bx
        push es
        in  al, 60h             ; 读扫描码
        pushf                   ; 模拟 int 的中断现场（iret 要弹标志）
        call dword ptr cs:[200H]    ; 调用原 int 9 例程（它发 EOI）
        ; ---- 自定义功能：在屏幕中间显示扫描码 ----
        mov ax, 0b800H
        mov es, ax
        mov bx, 160*12+40*2
        mov byte ptr es:[bx], 'a'
        ; ----
        pop es
        pop bx
        pop ax
        iret

Self-interruption routines ** without calling the original int 9 routine** (self-processed, not interrupted by the end of the original routine) must be sent EOI to the 20H port and return to iet before the end; if the routine is passed call dword ptr Call original routine, EOI sent by original routine,** no need to repeat.**

Experiment 15 Install new int 9 aborted routine

• Full installation and validation of the new int9 routine (keys to show scanning codes).

16. Direct location forms

16.1 Description of the number of the unit length

There are two labels in the code:

• ** Address number**: only a paragraph address: offset address (if s:) with no length properties;
• ** Data symbol**: both address and unit length:

a db 1,2,3,4,5,6     ; a 既代表地址（偏移 0），又代表字节单元
b dw 0               ; b 代表一个字单元的地址（偏移 6）
mov al, a[0]         ; = mov al, cs:[0]，编译器知道按字节取
mov ax, b            ; = mov ax, cs:[6]，按字取

16.2 Use of data labels in other paragraphs

• Use assume When the paragraph is linked to the paragraph register, the compiler automatically inserts the corresponding paragraph prefix** upon access to the data label in the paragraph; if there is a lack of conformity, the program is wrong, and it must set the paragraph register itself in the code.
• A prefix can also be given manually and visibly (e.g. ds:b）。

16.3 Direct location forms

** Direct address sheet**: indexed with data (e.g. numbering, character code) to obtain the target data/ address directly by means of a checklist, avoiding a long series of cmp condition branches.

** Numerical Table **: If marked with hexadecimal digit 0~F, check a character table to obtain the corresponding characters directly:

table db '0123456789ABCDEF'
; al 中为 0~F 的数值
mov bl, al
mov bh, 0
mov al, table[bx]    ; 直接查出对应字符的 ASCII

16.4 Direct address of the programme entry address

• Insert the entry of a group of sub-procedures sequentially into the table, numbered call word ptr table[bx] Direct assignment, standard formula for “multifunctional interruption routine”.

Experiment 16 Develop a break routine with multiple functional subprograms

• Use the entry list to achieve multifunctional disruption routines.

17. Keyboard input and disk reading and writing using BIOS

17.1 Int 9 interrupts the processing of keyboard input

Int 9 routine places key conversion in ** keyboard buffer zone** (ring queues with a maximum of 15 keys saved) for subsequent application; status buttons such as Shift/ CapsLock change status bytes.

17.2 Reading keyboard buffers using int 16h cut-off routines

BIOS provides int 16h keyboard interruption:

| Oh, my God. |----|------| | 0 | Read a keyboard input (a key removed from the buffer zone** and removed**; an empty buffer zone** awaits**). Result:ah = scan code, al = ASCII code | 1 | Query Buffer (** not removed**): Key ZF=0, Key ZF=1 | | 2 | Read Keyboard Status Bytes to al (Shift/ Ctrl/ CapsLock etc.) |

mov ah, 0
int 16H        ; 结果：ah = 扫描码，al = ASCII 码

17.3 String input

Accomplishing string input requires processing: character entry/cache, displaying resonance, retreating (delegate the top of the stack and erase screen characters) and returning to the end of the car. Core cycle (structure reference course 17.4, charstack for barber buffers and displays):

getstr: push ax
getstrs:
        mov ah, 0
        int 16h
        cmp al, 20h         ; ASCII < 20H 的控制键
        jb nochar
        mov ah, 0
        call charstack      ; 字符入栈
        mov ah, 2
        call charstack      ; 显示
        jmp getstrs
nochar: cmp ah, 0eh         ; 退格键的扫描码
        je backspace
        cmp ah, 1ch         ; 回车键的扫描码
        je enter
        jmp getstrs
backspace:
        mov ah, 1
        call charstack      ; 出栈
        mov ah, 2
        call charstack      ; 显示
        jmp getstrs
enter:  mov al, 0
        mov ah, 0
        call charstack      ; 0 入栈
        mov ah, 2
        call charstack      ; 显示
        pop ax
        ret

17.4 Read disks using int 13h interruption routine Write

BIOSint 13h access disk/hard disk with parameters agreed:

| Repository. |--------|------| | h | Function: 2 Read sector, 3 writing sector | | Number of sectors read and written at al | | c | Magnetic (column) | cl | sector number (starting with 1) | dh Magnetic head (node) | dl | drive (Floppy A 0, hard drive from 80H) | | Data buffer first address

; 从 0 号软驱 0 面 0 道 1 扇区读 1 个扇区到 es:bx
mov ax, data
mov es, ax
mov bx, 0
mov ah, 2
mov al, 1
mov ch, 0
mov cl, 1
mov dh, 0
mov dl, 0
int 13H

• Operation success: CF = 0, AH = 0, AL = number of actually read and write sections; failure: CF = 1, AH is the wrong code.
• Disk access to three elements:** magnetic track (column), magnetic head (face), sector**, which is the smallest unit to read and write the disk.

Experiment 17 Preparation of an interrupted routine with multiple functional subprograms

• Integrated keyboard input and disk reading and writing multifunctional break routines.

Comprehensive study

The five studies at the end of the course were conducted around the “C Language and Compilation Interface” (direct use of compilation capacity in C environments).

Research experiment 1 to create a streamlined C language development environment

• A compact C language development environment is built with a compendium to achieve minimum running support.

Research experiment 2 Use the register

• C directly uses the 8086 repository (depositor variables/inline compilation).

Research experiment 3 Use memory space

• Read and write the specified memory address space directly in the C language.

Study Test 4 does not program the Main function.

• Do not write the Main function, directly specify the programming method for the program entry.

Study how test 5 functions receive variable numbers of parameters

• Combining the ink transfer mechanism to understand how the C function receives an variable number of parameters (responding to note 4).

Notes

Note 1 Three working modes for the Intel series microprocessors

| Model |------|------| | ** Actual mode** 8086 Working mode, sector address x 16+ offset to 20-bit physical address with direct access to physical memory (full content of this course) | | Protection mode | 80286 introduced, paragraph repository segment selection sub, transformation of address by paragraph descriptor, supporting privileges and page breaks | Virtual 8086 mode 80386 introduced, model simulation under protection mode allowing multiple 8086 programs to run together

Note 2

• Negative $-X$ = $2^N - X$(N in bits); for replenishment: ** inverse plus 1**.
• 8-bit patch range -128127; 16-bit -32763276. Intra-CPU uniform symbol subtraction is achieved by supplementation.

Note 3 Related treatment of jmp by compiler (masm.exe)

• jmp short 标号 / jmp near ptr 标号:masm calculation offset = mark offset - offset of the first command after the jmp command, write the machine code;
• jmp far ptr 标号:masm directly writes the sector and offset addresses to the machine code;
• Off-short range. jmp short, the compilation is incorrect; it is the same as beyond the near;
• jmp 标号 Other Organiser

Note 4 Transfer parameters by stack

The use of incubation in advanced language (C) calls functions: callers turn parameters** from right to left ** and then press the incubation call; sub-apps bp Access Parameters[bp+4] For the first parameter,[bp+2] Is returned to IP,[bp+0] It’s saved old bp, caller balance post return (or use) ret n Balance by the caller.

Retrieval.

The following is a supplementary compilation of the notes, which is not part of the catalogue of educational materials, for quick review before the examination.

Depositary summary

The effect of the command on the mark

We’re gonna have to check the test quickly.

Let’s go through it for the last time.

1. ** There is no difference between instructions and data memory** and how they are currently used in CPU.
2. ** Paragraph is a logical concept** and the starting address of the paragraph must be a multiple of 16, with a long maximum of 64KB.
3. ** Small end**: word bytes at low address; stacks from high to low address, push first SP-2.
4. mov cannot give an immediate number of paragraph senders, to be passed through the universal register; two memory units cannot be transmitted directly.
5. Source Program [0] It’s an immediate count. ds:[0];debug [0] It’s memory.
6. Assume does not fill the field register, DS/SS does its own mov, CS:IP by end 入口 Automatic settings.
7. CF to look unsigned, OF to see signs spill, both separate; Inc/dec does not affect CF.
8. Conditional shift: no symbol b/a (below/above), symbol l/g (less/greater).
9. ** Interrupted vector table by 4 bytes: lower IP, high-word CS**, N interrupted at 0:Nx4 .
10. Interrupting process hardware automatically: pushf →TF=0, IF=0 →push CS, push IP → Jump; iret is the reverse.
11. ** div commercial excretion spill triggers break 0**; moul/div cannot be immediately counted.
12. 8086 migrations can only be 1 or cl; break code = code + 80H.
13. EOI is sent by (original)int 9 routine; self-writing is required when the original routine is not called.
14. Int 16H ah = 0, this key** in the buffer zone** has been removed; int 21H 01H waits and returns, 07H does not return.

** All book main line**: Removable memory segment location Quick address transfer and sub-programming system (Interrupted internal →int → port external **) Grab the four lines of “CPU how to use the CS:IP finger, DS/bx address, SS:SP to manage the inn, break the vector scale to find a routine” and all chapters can be linked.